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Showing posts from February, 2023

FUNCTIONAL COVERAGE OF PCIe MODULE Using System Verilog and UVM

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During my internship in 2019 , I got to work on Functional Coverage of PCIe block in a high speed module. Along with developing the functional coverage code , I have captured how to analyze results in VCS Verdi tool and do preliminary debugs in this following PDF . Enjoy !

Validation using OVM testbench for self-designed RTL module.

 During the beginning of my internship , I decided to ramp up on Testbench development and hence decided to create this mini project to learn and execute.  Disclaimer : Please excuse any flaws in the code , as this was created at very start of my career and I have not touched or corrected this ever since, so that I can compare how far I have come. Click this link to run the code on EDA :  https://www.edaplayground.com/x/DJ3A